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CXD2428Q
Video Scan Converter
Description The CXD2428Q is an IC which generates control signals and performs line interpolation calculations for field memory (CXK1206AM/ATM) in order to perform video signal scanning line conversion. In addition, this IC performs the aspect conversion of the ZOOM mode and WIDE-ZOOM mode in order to support wide screens. 100 pin QFP (Plastic)
Features * Video signal (NTSC/PAL) scanning line conversion function * ZOOM function (Function to cut top and bottom areas of 4:3 image and expand it to 16:9) * WIDE-ZOOM function (Function to vertically compress 4:3 image and expand it to 16:9) * Operating frequency: 28.6MHz (typ.) Absolute Maximum Ratings (Ta = 25C) * Supply voltage VDD VSS - 0.5 to +7.0 * Input voltage VI VSS - 0.5 to VDD +0.5 * Output voltage VO VSS - 0.5 to VDD +0.5 * Operating temperature Topr -20 to +75 * Storage temperature Tstg -55 to +150 Operating Conditions Supply voltage
V V V C C
VDD
4.5 to 5.5
V
Applications Liquid crystal projectors, etc. Structure Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E95442-ST
CXD2428Q
Block Diagram
TST0
TST1
TST2
3 28 53 78 CSD0 52 CSD1 55 CSD2 56 CSD3 57 CSD4 58 CSD5 59 CSD6 60 CSD7 61 CFD0 62 CFD1 63 CFD2 64 CFD3 66 CFD4 67 CFD5 68 CFD6 69 CFD7 70 YSD0 71 YSD1 72 YSD2 73 YSD3 74 YSD4 75 YSD5 76 YSD6 77 YSD7 80 YFD0 81 YFD1 82 YFD2 83 YFD3 84 YFD4 85 YFD5 86 YFD6 87 YFD7 88 BLNK 16
4 15 29 40 54 65 79 90
6 11 14 17 18 19 51 12 13 FSL1 FSL2
TST3
VDD1
VSS4
TST4
TST5
VDD2
VSS0
VSS5
TST6
VDD0
VDD3
VSS2
VSS3
VSS1
VSS6
VSS7
93 ADCK 94 ODEV H-WRITE 96 HIN 98 CKI 99 RYOE 100 BYOE
21 HOUT 22 HBLK H-READ 45 RDCK 95 HRET 89 HCR0 V-WRITE INTERPOLATION 91 VCR0 92 WEN0 97 VIN 10 VBLK 20 VOUT 46 REN1 V-READ 47 48 VCR1 HCR1
49 INC1 50 INC2 1 2 COEFFICIENT SERIALINTERFACE 5 7 8 9 1/2 SCLK SCTR SDAT P0 P1 P2
23 24 25 26 27 30 31 32
33 34 35 36 37 38 39 41
42 43 44
YD4
CD5
CD6
CD0
CD7
CD1
YD6
YD5
CD2
YD7
YD1
YD0
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RYCK
BYCK
YCK
CD4
CD3
YD3
YD2
CXD2428Q
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Symbol SCLK SCTR VDD0 VSS0 SDAT TST0 P0 P1 P2 VBLK TST1 FSL1 FSL2 TST2 VSS1 BLNK TST3 TST4 TST5 VOUT HOUT HBLK CD7 CD6 CD5 CD4 CD3 VDD1 VSS2 CD2 CD1 CD0 YD7 YD6 YD5 YD4 YD3 I/O I I -- -- I O I/O I/O I/O O I I I I -- I I I I O O O O O O O O -- -- O O O O O O O O Serial transfer clock Serial transfer control Power supply GND Serial transfer data Leave open. I/O port I/O port I/O port Vertical blanking output Fixed to high. Field identification selection (High: internal, Low: external) Field information polarity switching Fixed to low. GND Output data control (High: black display) Fixed to high. Leave open. Leave open. Vertical sync signal output Horizontal sync signal output Horizontal blanking signal B-Y/R-Y data output (MSB) B-Y/R-Y data output B-Y/R-Y data output B-Y/R-Y data output B-Y/R-Y data output Power supply GND B-Y/R-Y data output B-Y/R-Y data output B-Y/R-Y data output (LSB) Y data output (MSB) Y data output Y data output Y data output Y data output -3- Description
CXD2428Q
Pin No. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74
Symbol YD2 YD1 VSS3 YD0 BYCK RYCK YCK RDCK REN1 VCR1 HCR1 INC1 INC2 TST6 CSD0 VDD2 VSS4 CSD1 CSD2 CSD3 CSD4 CSD5 CSD6 CSD7 CFD0 CFD1 CFD2 VSS5 CFD3 CFD4 CFD5 CFD6 CFD7 YSD0 YSD1 YSD2 YSD3
I/O O O -- O O O I I O O O O O I I -- -- I I I I I I I I I I -- I I I I I I I I I Y data output Y data output GND Y data output (LSB) DA converter (B-Y) clock output DA converter (R-Y) clock output DA converter clock input Readout clock input Readout memory enable Readout memory vertical clear Readout memory horizontal clear Readout memory line increment Readout memory line increment Fixed to high. B-Y/R-Y lower line data input (LSB) Power supply GND B-Y/R-Y lower line data input B-Y/R-Y lower line data input B-Y/R-Y lower line data input B-Y/R-Y lower line data input B-Y/R-Y lower line data input B-Y/R-Y lower line data input
Description
B-Y/R-Y lower line data input (MSB) B-Y/R-Y upper line data input (LSB) B-Y/R-Y upper line data input B-Y/R-Y upper line data input GND B-Y/R-Y upper line data input B-Y/R-Y upper line data input B-Y/R-Y upper line data input B-Y/R-Y upper line data input B-Y/R-Y upper line data input (MSB) Y lower line data input (LSB) Y lower line data input Y lower line data input Y lower line data input -4-
CXD2428Q
Pin No. 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Symbol YSD4 YSD5 YSD6 VDD3 VSS6 YSD7 YFD0 YFD1 YFD2 YFD3 YFD4 YFD5 YFD6 YFD7 HCR0 VSS7 VCR0 WEN0 ADCK ODEV HRET HIN VIN CKI RYOE BYOE
I/O I I I -- -- I I I I I I I I I O -- O O O I O I I I O O Y lower line data input Y lower line data input Y lower line data input Power supply GND Y lower line data input (MSB) Y upper line data input (LSB) Y upper line data input Y upper line data input Y upper line data input Y upper line data input Y upper line data input Y upper line data input Y upper line data input (MSB) Write memory horizontal clear GND Write memory vertical clear Write memory enable AD converter clock Field information input Phase comparison output Horizontal sync signal input Vertical sync signal input Write clock input AD converter (R-Y) enable AD converter (B-Y) enable
Description
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CXD2428Q
Electrical Characteristics DC Characteristic Item Input, output voltage Input voltage 1 Symbol VI, VO VIH VIL VIH VIL VOH1 IOH = -2mA IOL = 4mA VOH1 IOH = -4mA IOL = 8mA VOH1 IOH = -6mA IOL = 12mA ILI1 Input leak current ILI2 ILI3 ILI4 Output leak current ILZ VIN = VSS or VDD VIN = VSS VIN = VDD VIN = VSS or VDD VIN = VSS or VDD VDD = 5.0V -10 -40 40 -40 -40 70 -100 100 VDD - 0.8 0.4 10 -240 240 40 40 VDD - 0.8 0.4 VDD - 0.8 0.4 0.8VDD 0.2VDD Conditions (VDD = 5.0V 0.5V, VSS = 0V, Topr = -20 to +75C) Min. Vss 0.7VDD 0.3VDD Typ. Max. VDD Unit V V 1 2 3 4 5 6 7 8 9 10 Applicable pin
Input voltage 2
V
Output voltage 1
V
Output voltage 2
V V A A A A A A mA
Output voltage 3
Current consumption IDD 1 2 3 4 5 6 7 8 9 10
All input pins other than 2 Pins 1, 2, 5, 96 and 97 All output pins other than 4 and 5 Pins 10, 22, 42, 43, 46 to 50, 89, 91, 92 and 93 Pins 20 and 21 All input pins other than 7, 8 and 9 Pins 11, 12, 19 and 51 Pins 13, 14, 16, 17 and 18 Pins 7, 8 and 9 Pin 6
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CXD2428Q
I/O Pin Capacitance Item Input pin capacitance Output pin capacitance Input/output pin capacitance Symbol CIN COUT CI/O Min.
(VDD = VI = 0V, f = 1MHz) Typ. Max. 9 11 11 Unit pF pF pF
Serial Block AC Characteristics
tw1 SCLK tw1
ts1 SDAT
th1
ts0 SCTL
th0
(VDD = 5.0V 0.5V, VSS = 0V, Topr = -20 to +75C) Symbol ts1 th1 tw1 ts0 th0 Item Setup time of SDAT in relation to the rise of SCLK Hold time of SDAT in relation to the rise of SCLK SCLK pulse width Setup time of SCTL in relation to the rise of SCLK Hold time of SCTL in relation to the rise of SCLK Min. 100ns 100ns 100ns 100ns 100ns 2tw1 2tw1 Max.
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CXD2428Q
AC Characteristics
CKI RDCK tpd max tpd min
Output
invalid Input
ts2
th2
1) Output block Item Delay of ADCK in relation to CKI Delay of HCR0, VCR0 and WEN0 in relation to CKI
(VDD = 5.0V 0.5V, VSS = 0V, Topr = -20 to +75C) tpd min 3ns 10ns 6ns 5ns 7ns 1ns 5ns 5ns 2ns tpd max 28ns 70ns 32ns 30ns 45ns 22ns 38ns 32ns 25ns Load 20pF Load 25pF Condition
Delay of REN1, VCR1, HCR1, INC1 and INC2 in relation to RDCK Delay of HOUT in relation to RDCK Delay of VOUT in relation to RDCK Delay of RYCK and BYCK in relation to YCK Delay of YD0 to YD7 and CD0 to CD7 in relation to RDCK Delay of HRET in relation to CKI Delay of BYOE and RYOE in relation to CKI
2) Input block Item Setup and hold time of CSD0 to CSD7, CFD0 to CFD7, YSD0 to YSD7 and YFD0 to YFD7 in relation to RDCK Setup and hold time of HIN in relation to CKI Setup and hold time of VIN in relation to CKI Setup and hold time of YCK in relation to CKI ts2 9ns 3ns 0ns 20ns th2 3ns 3ns 20ns 2ns
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CXD2428Q
Description of Operation 1. CXD2428Q Control System The operation timing of this IC is controlled by serial data. An 8-bit address and 8-bit data are sequentially transferred from the falling edge of SCTL, and each control data is taken in at the rising edge of SCLK up to the rising edge of SCTL.
SCLK
SCTL
SDAT
ADDRESS
DATA
Serial transfer timing
2. Control Mode The following timing and modes are changed by control data: Variable H SHIFT V SHIFT H PHASE V PHASE H SZ RD H SZ WR LN DAT0 to 7 MD DAT0 to 7 TOP BLK BTM BLK LFT BLK RGT BLK IODAT IOSL TEST Address 00H 10H 20H 30H 40H 50H 41H 51H 60 to 67H 70 to 77H A0H B0H C0H D0H 80H E0H 90H Function Horizontal write start timing Vertical write start timing Horizontal readout start timing Vertical readout start timing Number of readout line dots (0 to 7 bits) Number of readout line dots (8 to 10 bits) Number of write line dots (0 to 7 bits) Number of write line dots (8 to 10 bits) Conversion mode address Conversion mode data Vertical blanking rise timing Vertical blanking fall timing Horizontal blanking rise timing Horizontal blanking fall timing I/O port output data1 OUT port select2 3
1 Transfer xxxx.1xxx (binary) for PAL (4:3 display) and xxxx.0xxx (binary) for the other systems. 2 Transfer 00 (hexadecimal). 3 Transfer 00 (hexadecimal). -9-
CXD2428Q
3. Scanning Line Conversion Function LN DAT (address 6x) and MD DAT (address 7x) are data which indicate scanning line conversion coefficients. There are the following 8 conversion coefficients: 1.67/1.75/2/2.22/2.33/2.67/2.8 = K K= number of scanning lines of output signal number of scanning lines of input signal
The conversion coefficient equals the ratio of one scanning line to scan lines generated by interpolation. The coefficient can be changed on the screen. In the WIDE-ZOOM mode, compression and expansion on the screen can be changed by combining these 8 coefficients as desired. Compression and expansion are carried out by setting the coefficient and the number of switching lines. The upper 6 MD DAT bits (bits 3 to 8) provide coefficient data. The lower 2 MD DAT bits (bits 1 and 2) and 8 LN DAT bits provide line number data. The coefficients and corresponding MD DAT are shown below. Coefficient 1.67 1.75 2.0 2.1 2.22 2.33 2.67 2.8 MD DAT MSB LSB 000100xx 001000xx 000001xx 000000xx 010000xx 011100xx 101000xx 110000xx 110110xx
The interpolation coefficient 2.0 has two modes which are determined by the value of bit 3. When bit 3 is 1, an interpolation line is generated by outputting the same signal as that of the preceding line. This mode realizes images with a higher vertical resolution. When bit 3 is 0, an interpolation line is output by averaging signals of the preceding and following lines. This mode realizes images with smoother diagonal lines.
4. DA Converter Clock RYCK and BYCK, which are YCK halved and phase inverted, are output as D/A converter clocks. 5. Output Control A black signal is output when BLNK is high.
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CXD2428Q
Mode Setting and Operation 1. Horizontal Write CKI is input after phase comparison with HSYNC input. PLL frequency division value is set by H SZ WR (standard 38C (hexadecimal)), and HRET is output. Write start timing is set by H SHIFT. An ADCK pulse, which is CKI halved, is output. The enable pulses RYOE and BYOE for R-Y and B-Y A/D converter are output.
HIN
HRET
H SZ WR + 2ck
HWEN (Internal pulse) (H SHIFT + 1) x 2ck
HCR0
RYOE
BYOE
CKI
ADCK
RYOE
BYOE
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CXD2428Q
2. Horizontal Readout In this IC, the readout and write clocks are asynchronous. The readout 1H sample coefficient is set by H SZ RD. An HOUT pulse with a pulse width of 68ck is output from horizontal readout reference pulse HRSP (internal pulse). Readout start timing is set by H PHASE. The HBLK pulse set by LFT BLK and RGT BLK is output. However, this pulse does not stop readout, so it has no relation to the actual blanking interval.
HRSP H SZ RD + 2ck
HOUT
68ck
HREN (Internal pulse) H PHASE + 2ck
HBLK LFT BLK + 2ck RGT BLKck
HCR1
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CXD2428Q
3. Vertical Write Write start timing is set by V SHIFT. The CXK1206AM/ATM write control pulses VCR0, HCR0 and WEN0 are output.
HIN
VIN
VSP (Internal pulse)
V SHIFT + 1H
VWEN (Internal pulse)
VCR0
HCR0
WEN0
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CXD2428Q
4. Vertical Readout The VBLK pulse set by TOP BLK and BTM BLK is output. However, this pulse does not stop readout, so it has no relation to the actual blanking interval. Readout start timing is set by V PHASE. The CXK1206AM/ATM readout control pulses VCR1, HCR1, REN1, INC1 and INC2 are output. The VSP pulse (internal pulse) corresponding to V SHIFT is the vertical readout reference pulse. A VOUT pulse with a pulse width of 6H ( indicates double scan H) is output.
HOUT
VSP (Internal pulse)
VOUT
6H Note 1) Note 1) PAL (4:3): 65H, Others: 0H
VREN (Internal pulse)
V PHASE + 1H
TOP BLK + 1H VBLK 320 + BTM BLKH
VCR1
HCR1
REN1
Note 2) INC1 and INC2 timing varies with modes. INC1
INC2
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CXD2428Q
Application Circuit
CAD YAD +5V +5V
0.1
0.1
Y07 Y06 Y05 Y04 HCR1 INC2 VCR1 REN1 Y97 Y96 Y95 Y94
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
VSS VDD NC NC APM CKW0 PW HCLR0 DIN3 INC0 DIN2 VCLR0 DIN1 WE DIN0 HCLR1 HCLR2 INC1 INC2 VCLR1 VCLR2 OE1 OE2 DO13 DON23 DO12 DO22 DO11 DO21 DO10 DO20 CKR1 CKR2 TSM TR2 TR1 VSS TR0 CXK1206
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
HCR0 VCR0 WEN0 HCR1 INC1 VCR1 REN1 Y87 Y86 Y85 Y84
C07 C06 C05 C04 HCR1 INC2 VCR1 REN1 C97 C96 C95 C94
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
VSS VDD NC NC APM CKW0 PW HCLR0 DIN3 INC0 DIN2 VCLR0 DIN1 WE DIN0 HCLR1 HCLR2 INC1 INC2 VCLR1 VCLR2 OE1 OE2 DO13 DON23 DO12 DO22 DO11 DO21 DO10 DO20 CKR1 CKR2 TSM TR2 TR1 VSS TR0 CXK1206
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
HCR0 VCR0 WEN0 HCR1 INC1 VCR1 REN1 C87 C86 C85 C84
10k x 4
10k x 4
10k x 4
10k x 4
+5V
+5V
0.1
0.1
Y03 Y02 Y01 Y00 HCR1 INC2 VCR1 REN1 Y93 Y92 Y91 Y90
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
VSS VDD NC NC APM CKW0 PW HCLR0 DIN3 INC0 DIN2 VCLR0 DIN1 WE DIN0 HCLR1 HCLR2 INC1 INC2 VCLR1 VCLR2 OE1 OE2 DO13 DON23 DO12 DO22 DO11 DO21 DO10 DO20 CKR1 CKR2 TSM TR2 TR1 VSS TR0 CXK1206
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
HCR0 VCR0 WEN0 HCR1 INC1 VCR1 REN1 Y83 Y82 Y81 Y80
C03 C02 C01 C00 HCR1 INC2 VCR1 REN1 C93 C92 C91 C90
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
VSS VDD NC NC APM CKW0 PW HCLR0 DIN3 INC0 DIN2 VCLR0 DIN1 WE DIN0 HCLR1 HCLR2 INC1 INC2 VCLR1 VCLR2 OE1 OE2 DO13 DON23 DO12 DO22 DO11 DO21 DO10 DO20 CKR1 CKR2 TSM TR2 TR1 VSS TR0 CXK1206
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
HCR0 VCR0 WEN0 HCR1 INC1 VCR1 REN1 C83 C82 C81 C80
10k x 4
10k x 4
10k x 4
10k x 4
Y96 Y95 Y94 Y93 Y92 Y91 Y90 C87 C86 C85 C84 C83
Y97
C82 C81 C80 C97 C96 C95 C94 C93 C92 C91
C90
0.1
10 16V
+5V
80 7978 7776 7574 7372 7170 6968 6766 6564 6362 6160 5958 5756 5554 5352 51 YSD7 VSS6 VDD3 YSD6 YSD5 YSD4 YSD3 YSD2 YSD1 YSD0 CFD7 CFD6 CFD5 CFD4 CFD3 VSS5 CFD2 CFD1 CFD0 CSD7 CSD6 CSD5 CSD4 CSD3 CSD2 CSD1 VSS4 VDD2 CSD0 TST6 Y80 Y81 Y82 Y83 Y84 Y85 Y86 Y87 HCR0 VCR0 WEN0 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 YFD0 YFD1 YFD2 YFD3 YFD4 YFD5 YFD6 YFD7 HCR0 VSS7 VCR0 WEN0 ADCK ODEV HRET HIN VIN CKI RYOE BYOE INC2 INC1 HCR1 VCR1 REN1 RDCK YCK RYCK BYCK YD0 VSS3 YD1 YD2 YD3 YD4 YD5 YD6 YD7 CD0 CD1 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 INC2 INC1 HCR1 VCR1 REN1
28.6MHz YCLK R-YCLK B-YCLK
YDA0 YDA1 YDA2 YDA3 YDA4 YDA5 YDA6 YDA7
CXD2428Q
HD VD CKI
SCLK SCTR VDD0 VSS0 SDAT TST0 P0 P1 P2 VBLK TST1 FSL1 FSL2 TST2 VSS1 BLNK TST3 TST4 TST5 VOUT HOUT HBLK CD7 CD6 CD5 CD4 CD3 VDD1 VSS2 CD2 10 16V
1 2 3 4 5 6 7 8 9 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 30
0.1
+5V
SIO
SCLK SCTR SDAT
CDA2 CDA1 CDA0
CDA7 CDA6 CDA5 CDA4 CDA3
YDA CDA HRCK HOUT VOUT VBLK B-YOE R-YOE HRET ADCK
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
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CXD2428Q
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
+ 0.1 0.15 - 0.05
23.9 0.4 + 0.4 20.0 - 0.1
+ 0.4 14.0 - 0.01 17.9 0.4
15.8 0.4
A
0.65 0.12 M
+ 0.35 2.75 - 0.15
0.15
0 to 15 DETAIL A
0.8 0.2
(16.3)
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.4g
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